Design, Implementation, and Functional Verification of a Single-Cycle 8-Bit RISC Processor Based on Von Neumann Architecture

Abstract

Computer architecture is fundamentally grounded in the core principles of Computer Organization and Architecture (COA), including digital logic design and the structural configuration of processing units. For students to fully comprehend these concepts, theoretical instruction alone is often insufficient; practical exposure through simulation significantly enhances understanding. One effective method is the development of a simple 8-bit Central Processing Unit (CPU) model that demonstrates how architectural components interact in real time. The proposed design follows the Von Neumann architecture model, incorporating essential elements such as registers, a bus interface, an Arithmetic Logic Unit (ALU), and memory, along with their internal interconnections. The CPU simulation is implemented using Logisim, a digital logic simulation tool that enables users to construct and test circuits efficiently. Logisim supports hierarchical circuit design, allowing small combinational and sequential subcircuits to be integrated into a fully functional CPU within a unified environment. Undergraduate students frequently encounter difficulties when studying COA concepts solely through textbooks and lectures, as traditional teaching methods often describe system architecture without demonstrating the dynamic, step-by-step operational flow. To address this gap, this research presents the systematic design and implementation of an 8-bit CPU in Logisim, inspired by the simplified Mic-1 model. The stepwise construction approach helps students visualize how individual components contribute to overall processor functionality, thereby strengthening conceptual understanding before progressing to more complex, application-specific computer designs.